A Promising Approach to Overcome the Verification Gap of Modern SoC Designs
This paper describes a new verification methodology that has been successfully used for the development of a complex multiple-port system controller. The controller provides bridging functions, among various bus interfaces, and heterogeneous memory configurations....
Accelerated Verification Process Automation
A wide variety of technology is available today to describe and model the behavior of system-level devices, from high-level and abstract architectural modeling languages, to hardware description languages running in software simulators, to hardware acceleration and beyond....
ACT and AHB eVC
Functional verification is the biggest challenge in designing complex systems today. State-of-the-art verification approaches employ techniques like directed-random generation, data and assertion checking, and functional coverage analysis....
Advancing HW/SW Co-Verification Methodology
The term hardware/software (HW/SW) co-verification was coined in the mid 1990s to describe a process that allows embedded system software to be executed on a simulated representation of the hardware design....
Assertion Processor
Assertion-based verification methodologies are the next breakthrough in design verification. When this methodology is combined with a high-performance verification platform, design teams can meet the challenges of the next generation of complexity....
Co-Verification Debugger Enables Hardware and Software Communication for SoC Verification
Effective and efficient co-verification methodology for SoC verification requires a single platform with logic simulation, simulation acceleration, and in-circuit emulation and application-specific solutions for co-verification and transaction-based verification...
Coverage-Driven Functional Verification
In an ASIC design house in the United States, a verification engineer wanted to measure the completeness of his verification test suite using functional coverage. The VHDL testbench and design were mature, and the test suite was comprised of assembly code tests which were manually written in three man year's of work....
Emulating Behavioral Objects
Simulation acceleration and emulation products are seeing a dramatic upsurge in popularity because designs are getting so large that it takes days, weeks and even months to run the tests that are needed to verify the design...
Functional Verification Automation for IP
The development and integration of intellectual property (IP) in the form of large functional blocks, or cores, is an essential part of an increasing number of today's IC design strategies. Numerous benefits justify this approach....
Hardware/Software Co-Verification of Embedded Systems Design
One of the most critical steps of embedded system design is the integration of software with hardware. Traditionally, this important step has been performed in a lab environment by constructing hardware prototype....
In-Circuit Verification (ICV) Unifying Simulation and Emulation
This paper introduces a new methodology known as In-Circuit Verification (ICV). It defines the three unique modes of ICV and helps you to understand how to logically transition across these modes from simulation to emulation by minimizing the number of variables introduced during the transitions....
Platform Verification
Platform verification is a new methodology for verifying system-on-a-chip (SoC) and system-level designs. Analogous to platform design, platform verification is an integrated functional verification system supporting all levels of abstraction concurrently throughout the entire design flow...
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Practical Approaches to SOC Verification (DATE 2000 Paper) (PDF)
This paper provides some guidelines on how to approach System On a Chip (SOC) verification, and how to create effective SOC testbenches. It surveys the challenges in SOC verification and some of the traditional verification techniques, and then focuses on showing preferred practical approaches....
Processor-Based SOCs Pose New Hardware/Software Debugging Challenges
The potential for cutting costs and improving performance by designing advanced SoCs with embedded processors is limited by current SoC verification and debug equipment. New RCC-based development systems combine dual hardware and software simulation and emulation engines to provide detailed system characteristics and powerful debug features....
ReConfigurable Computing (RCC) For Logic Simulation
Fueled by advancements in semiconductor manufacturing capabilities, System-On-Chip (SoC) has become a reality with ever increasing demands for products to possess high performance, capacity and reliability....
ReConfigurable Computing Turbo-Charges (RCC) Simulation
In the future, RCC-simulation will be an even more important tool as the industry increasingly moves into reconfigurable applications. Reconfigurable systems are gaining greater momentum in many design camps, particularly in networking applications, which rely heavily on high density four to 10 million ASIC chips....
Spec-Based Verification
Due to the increasing complexity of today's ASICs and systems, functional verification has become a major bottleneck in the design process. Design teams reportedly spend as much as 50 to 70 percent of their time and resources on the functional verification effort....
Software Debugging Targeted At Embedded Software Designs
Today, more and more focus is being placed on system-level design, viewing the total project as a complete system instead of the individual parts: chips, boards, chassis, and software. Managers are looking for ways to shorten the project schedule and increase confidence in the design....
Testbench Acceleration
Verisity’s testbench acceleration methodology, which utilizes eCelerator’s synthesis technology, is a breakthrough in hardware-assisted verification. A synthesized e testbench provides a single environment, single language and single methodology whether you use pure software simulation or hardware-assisted verification....
Using Code Coverage with Verisity' RCC Technology
Simulation acceleration and emulation products are seeing a dramatic upsurge in popularity because designs are getting so large that it takes days, weeks and even months to run the tests that are needed to verify the design....
Verification Automation Management
vManager brings automation to a broad range of tasks in the verification process. For the verification engineer, vManager eases the administration and analysis of large simulation sessions, speeds the analysis of failures, and enhances all aspects of coverage analysis....
Verification Reuse Methodology
Verification managers engaged in complex IC development projects are under constant pressure to reduce the time and cost of verification, yet they lack the necessary resources. This white paper articulates how reusable verification components, and an underlying verification reuse methodology are essential elements to verification productivity gains.... |
