Processor-Based
SoCs Pose New Hardware/Software Debugging Challenges
SoCs with embedded processors
cut costs and potentially cut time to market, but present significant
new challenges in hardware/software integration and chip debugging.
Table of Contents
Overview
Advances in semiconductor manufacturing technology and design methodologies
are enabling the development of complex system-on-chip (SoCs) devices
with millions of transistors. Designers seeking to leapfrog the
competition with superior performance at lower cost are embedding
custom logic blocks and large third-party intellectual property
(IP) elements such as 32- and even 64-bit processor cores into large
single chip solutions. These solutions promise the twin advantages
of faster time to market and lower product costs, but come with
some significant new development and debug issues that threaten
the viability of SoCs.
Chief among these is the thorny problem of
accomplishing a fast simulation or accurate emulation of the final
system. Looming right behind is the task of providing effective
debug tools for unraveling the hardware/software integration problems
associated with complex single chip designs.
Facing down the challenge of accuracy of simulation,
speed of emulation and providing comprehensive debug tools is the
task ahead for the makers of cutting edge ASIC and SoC development
tools. Traditional tools associated with processor debug, Instruction
Set Simulators or ISSs, and bus functional models or BFMs, are simply
not up to the task. Traditional hardware emulators are fast, but
provide little or no debug support.
A new approach, the ReConfigurable Computing
coprocessor or RCC approach from Axis Systems Corp., attacks the
problem with an unique blend of simulation and hardware emulation
that solves all three problems simultaneously. It uses the concept
of instant replay for debugging by using a "hot-swap"
technique between "hardware emulation" and mirrored "software
simulation." This one of a kind approach combines the advantages
of hardware emulation, primarily for speed, and software simulation,
primarily for visibility and debug features. To this it adds system-wide
debugging advantages by capturing real system trace data while maintaining
the ability to accurately regenerate history of all node changes
from any point in the execution sequence.
Traditional Approaches
Suffer from Lack of Accuracy and Speed Deficiencies
The traditional tools for SoC development when using embedded processors
are Instruction Set Simulators and bus functional models. These
tools are proving inadequate for the job of complete system verification,
however. The ISS is a fixed architectural model of the core processor
and can only provide the simulation of the processor itself when
executing a single instruction at a time. It cannot understand how
the processor interacts with the rest of the system. Consequently,
it does not yield an accurate view of the total system. When a bus
functional model is added to the equation, the system level activity
view is a little broader, but still lacks any visibility into the
rest of the system because it only incorporates limited interaction
with the custom logic or any other processor in a multi-processor
system. Another problem for ISS and bus functional models is that
they cannot model the newer configurable processor cores, where
one can configure instructions for different applications. On the
positive side, ISS and BFMs are fast, typically in the 10,000 to
100,000 cycles per second range. On the negative side, they are
of questionable accuracy in predicting actual system response characteristics
under real-time, real-system conditions.
Current approaches add a Verilog or VHDL simulator
to the picture to provide simulation of the rest of the hardware
of the system-on-chip. Because the hardware description language
is derived from the actual design RTL, this has an advantage of
predicting operational characteristics very well. However, traditional
compiled HDL simulators running on workstations are slow, usually
in the 10 to 100 cycles per second range. Slowing down the debug
of processor driven systems to these slow cycle times makes debugging
a sluggish nightmare. Today's high performance embedded processors
are pushing into the 1 Gigahertz range and trying to wade through
a few thousand instructions at that rate can be maddeningly slow
and totally inadequate in predicting real-time system operation.
An alternative approach is to build custom
hardware prototypes that more accurately reflect the total system
design, using processor cores and FPGA devices to model the SoC
in hardware. This has the important benefit of far greater speed,
but provides no easy way to debug the resulting prototype-based
system. The prototype-based systems provide limited means to stop
and capture the resulting system activity. Even processors with
non-intrusive debug features, such as EJTAG, can only capture internal
processor information, not concurrent external custom logic states.
It is especially difficult to debug SoC systems with multiple processor
cores on prototype-based systems because they cannot stop all the
processors at the same time using the EJTAG mechanism.
Into this mix of inaccurate and slow software
solutions, and fast, but hard to debug hardware solutions, comes
a new approach, the RCC or ReConfigurable Computing coprocessor
architecture.
RCC Provides Both Speed and
Accuracy For Hardware/Software Integration
RCC systems are based on the idea of twin simulation and emulation
engines that operate in parallel and are "hot-swappable"
during a debug session. The accuracy of the design is based on the
fact that both hardware and software simulation engines are based
on the same source, a database that consists of the actual RTL (register
transfer level) design code used in the final design itself.
Working with the RTL database of the design,
RCC systems use a sophisticated software simulator to create a software
simulation of system activity. At the same time, using the same
RTL database, a hardware implementation of the system-on-chip is
created using the patented processor composition technology implemented
on FPGAs. This yields a fast, accurate system simulation and emulation
system.
But, this is not enough, because hardware and
software engineers still need comprehensive debug tools. This means
that they must have the means of setting complex trigger conditions,
for the hardware engineer, and precise breakpoints, for the software
engineer, and have visibility into the rest of the system at that
point in time.
For the hardware engineer, triggers result
in the capture of waveform data. The RCC captures debug information
throughout the entire execution up to the trigger point and has
the capability of regenerating waveforms in every node of the design
at any given point of time in the execution history.
Figure 1 - RCC system architecture
Caption - The RCC system is composed of
"Hot-swappable" twin software simulation and hardware emulation
engines.
For the software engineer, breakpoints result
in the capture of register states, data values, variable values,
and pointer information. From this information, the engineer can
determine where in a given procedure or loop the problem occurs
and the state of various processor elements at any given time. In
addition, for hardware/software integration, the state of the other
hardware elements of the system can also be analyzed at any given
breakpoint.
Figure 2 - The Hot-swap and replay mechanism
of RCC engine.Caption - The RCC system can hot-swap between simulation
and emulations engines to dump waveforms and replay the processor
activity from a trigger or a breakpoint.
This methodology yields a tremendous breakthrough
in reducing development time. With the power to execute application
code at emulation speed while capturing full debug information within
the software simulator, the RCC-based development tool gives the
hardware engineer, the software engineer, and the hardware/software
integration engineer the visibility required to complete development
and debug tasks rapidly.
How It's Done - Two Verification
Engines and A "Hot-Swap"
The simultaneous delivery of a fast, accurate development system
that includes complex hardware and software debugging tools seems
too good to be true. In fact, it takes some breakthrough technology
to create such a system, but it achievable, and at a cost less than
traditional prototype-based hardware emulation methods.
To accomplish the goal of a RCC-based development system, there
are two key core technologies required and one key design implementation
technique, hot-swapping.
The software core technology is a sophisticated
simulation engine that can simultaneously provide full debug features
and link to the hardware RCC engine. The hardware core technology
is the RCC engine that can provide a functional emulation of the
target system-on-chip, and link to the software simulation engine.
The critical ingredient is the ability to
hot-swap execution from the software engine to the hardware engine
and back again. It works something like this. When the system is
cruising through normal operation, the hardware engine is rev'ved
up and provides fast system emulation in hardware. When a hardware
trigger condition occurs (or a software breakpoint), the system
stops and switches into software engine mode. But wait! Isn't it
too late to switch back, once the trigger occurs?
Yes, and no. For here is where part of the
clever design of the RCC engine comes in. The RCC takes an initial
snapshot of the system at startup. After a given interval, the RCC
takes another snapshot of the system. Between snapshots, RCC logs
the entire input to the SoC system. At any given trigger point,
the system can go back to a previously captured snapshot of the
system and replay the system operation with the input log. For replay,
it uses the RCC engine to fast-forward the system state from the
snapshot to the point of interest and then hot-swaps to the software
simulation engine. At that point it uses the powerful debugging
features of the software simulation engine to link with both waveform
viewers and source code debuggers. This does the trick. The designer
now gets all of the system and state values needed for comprehensive
system development and debug.
For the hardware engineer, the RCC-based development
system provides full waveform information for points throughout
the system under development. The engineer can set triggers on any
selection of system level activity and pinpoint precise trouble
spots for in-depth analysis.
For the software engineer, the RCC-based development
system provides accurate instruction-by-instruction debug information
with the ability to set breakpoints on both internal value states
and external memory and system logic conditions. In addition, RCC
can instantaneously replay a full history of processor execution
for software debugging.
Summary
The potential for cutting costs and improving performance by designing
advanced SoCs with embedded processors is limited by current SoC
verification and debug equipment. New RCC-based development systems
combine dual hardware and software simulation and emulation engines
to provide detailed system characteristics and powerful debug features.
Such systems will enable faster SoC development and lower implementation
costs.
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