| Wednesday |
May 11, 2005 |
| 08:30 - 09:00 |
Registration and Continental Breakfast |
| 09:00 - 09:15 |
Welcome and Introduction
Steve Brown, Cadence Design Systems |
| 09:15 - 09:45 |
Keynote
Michael McNamara, Cadence Design Systems |
| 09:45 – 10:30 |
Verification for a Ghz DSP—Experience Designing an eRM-compliant Environment
Shoban Jagathesan, Texas Instruments |
| 10:30 – 10:45 |
Break |
| 10:45 - 11:30 |
vBuilder
Sharon Rosenberg, Cadence Design Systems |
| 11:30 – 12:15 |
In-Circuit Emulation Techniques for Pre-Silicon Verification
Anup Kumar Raghavan, Freescale Semiconductor |
| 12:15 – 12:30 |
Company Overview
Moshe Gavrielov, Executive Vice President, Cadence Verification Division |
| 12:30 – 14:00 |
Lunch Engineers Roundtable Discussions |
| 14:00 – 14:45 |
MPC8548/TS1568A Serial RapidIO Interoperability
Lan Nguyen, Freescale Semiconductor |
| 14:45 – 15:30 |
Towards IEEE P1500 Test Infrastructure eVC
Stylianos Diamantidis, Globetech Solutions |
| 15:30 - 15:45 |
Break |
| 15:45 – 17:00 |
Transaction Level Methodology in SoC Verification
Dean D’Mello and Stuart Swan, Cadence Design Systems |
| 17:00 – 18:30 |
Cocktail Reception |
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| Thursday |
May 12, 2005 |
| 08:00 – 08:30 |
Breakfast |
| 08:30 – 10:30 |
Tutorial - Verification Planning
Andrew Piziali, Cadence Design Systems |
| 10:30 – 10:45 |
Break |
| 10:45 – 11:45 |
Tutorial - Verification Planning (continued)
Andrew Piziali, Cadence Design Systems |
| 11:45 – 12:15 |
Scoreboard Design Using Method Ports
Pandy Kalimuthu, WIPRO Technologies |
| 12:15 -13:15 |
Lunch |
| 13:15 – 14:00 |
Verification of Mixed-Signal Systems
Matteo Martinelli, Yogitech SpA |
| 14:00 |
Closing Remarks
David Tokic, Cadence Design Systems |
