Xtreme-II The First Verification Environment for Platform Verification

Xtreme-II Benefits Extreme Versatility Seamlessly integrates emulation, acceleration, and simulation into a single verification environment Expands into multiple applications, such as assertion processors, code coverage, and testbench Provides a configurable platform for early system-level integration Emulates behavioral objects with reconfigurable behavioral processors High Capacity Supports designs of up to 100M ASIC gates Provides memory of up to 2.5GB High Performance Runs at speeds of up to 1M cycles per second Ease-of-Use Preserves the native simulation debugging environment by supporting all HDL constructs and PLI calls Integrated Debugging Tools Offers hot-swapping in real time from emulation to simulation for maximum debugging flexibility Extracts all design node history information during or after simulation using VCD-on- Demand (VoD) Pre-Compiled Model Linking Provides accurate modeling of event-based, cycle-based, and transaction-based modeling styles Links different levels of modeling abstraction into one verification environment

Verification Bottleneck
Until now, verification tools have not kept pace with the incredible rate at which design sizes are growing, creating a rapidly widening verification gap.

Traditional software simulation works well for architectural verification, but slows down significantly at RTL and gate level. Traditional hardware emulation achieves high performance, but takes you outside of your native simulation environment with steep learning curves, lengthy setup times, and difficult debugging methods.

To close the verification gap, Axis Xtreme-II provides emulation performance and simulation flexibility in a single system with a unified design database.

Platform Verification
Xtreme-II offers Platform Verification, a unified verification environment designed to enable a platform-based design flow.

Platform-based SoC designers can quickly create new, or modify existing, architectures much earlier in the design flow. Designers can leverage IPs from various marketplaces or re-use models created from previous projects.

Platform Verification enables early access to HW/SW system integration and demonstrates system performance before actual silicon is available.

Xtreme-II
Enabled by Axis' patented ReConfigurable Computing (RCC) technology, Xtreme-II offers the best solution for simulation, acceleration, and emulation in one unified system. By leveraging the latest FPGA technologies, Xtreme-II delivers fast runtime performance and the highest capacity, while preserving the native RTL simulation debugging environment.

In-Circuit Emulation
Xtreme-II can connect directly to a target system and is controlled through a Sun workstation via one set of PCI extender cables for compactness and high-speed communication.

The ability to simultaneously emulate physical hardware with software models, while using a software simulation environment for debugging, provides the most flexible and accessible system integration solution.

Behavioral Emulation and Procedural Callbacks
Xtreme-II extends emulation with behavioral processors and embedded procedural callbacks.

For the first time, a practical method for emulating non-synthesizable behavioral objects is made possible with behavioral processors. Xtreme-II's unique behavioral emulation capability maintains the performance level of emulation without giving up the flexibility of a software simulation environment.

Xtreme-II automates event-driven callbacks during acceleration or emulation. By using embedded callback options, you can use common simulation tasks or customized software utilities to process functions that are better handled by the workstation.

One-Step Compilation and Mapping
Design descriptions can be separated into three components: behavioral, RTL, and gates. The Xtreme-II compiler automatically maps sections that can be emulated with the RCC engine and builds a native-compiled simulation image for sections that remain in Xsim.

The patented Hierarchy Extracted mapping technique automatically maps the design onto arrays of FPGAs for optimized gate usage and high-performance simulation.

Debug in Software, Emulate or Accelerate in RCC
Xtreme-II's ability to hot-swap states between Xsim and the RCC engine, in real time, makes it unique among hardware verification systems.

During simulation, you can swap the state of the RCC engine into Xsim to debug the design and continue in software simulation. When your circuit is fully debugged, and the problem isolated, the simulation state value can be swapped back into the RCC engine for maximum simulation performance.

Complete History with no Re-simulation
Xtreme-II's VCD-on-Demand (VoD) feature provides access to all node history values from any point in simulation without re-simulating from time zero. This capability significantly increases design debugging productivity. Waveforms can be generated in either IEEE-standard VCD (Value-Change-Dump) or FSDB (Fast Signal Database) format.

Simplified Library and Memory Conversion
To maximize density and performance of the RCC processors, design library and memory cells are converted into RCC elements. For library cells, a library compiler will automatically generate appropriate mapping, along with library verification test vectors.

For embedded design memory blocks, you can configure Xtreme-II's large internal cache memory and on-board memory to the specific memory type. For complete system verification, large external memories can be integrated using the default extended memory board or workstation memory communicating via the fast PCI bus.

All-Encompassing System
To stay one step ahead of your competition, you need the fastest, most efficient, and most adaptable verification system available today. With solutions for simulation, acceleration, and emulation in a single verification system, Xtreme-II has been designed with you in mind—to significantly increase your verification productivity and confidence in your designs.

Xtreme-II Specifications
Architecture	ReConfigurable Computing (RCC) engine Event-based algorithm
Supported Operating Systems and HW Platforms	Sun Solaris: Sun Ultra 60, 80 Sun Blade 1000, 2000 Red Hat Linux: IBM x255 Series
Design Format	IEEE 1364-2001 Verilog IEEE 1076-1993 VHDL
Mixed HDL Logic Simulation	Single kernel Event look-ahead Native code compiled Single kernel
Software Interfaces	XMI-API PLI
Gate and I/O Capacities	Up to 100M ASIC gates Up to 1940 I/Os
Programmable Trigger Generators	Up to 1K probes per trigger Up to 48 separate trigger generators
Runtime Performance	Up to 1M cycles/sec
Memory	Up to 1780M bits of on-board RCC memory Up to 2.5GB of extended memory Up to 4GB of workstation memory
Debugging	Support for mixed HDL Graphical user interface Real-time logic simulation hot swapping between software and hardware VCD-on-Demand (VoD)

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