Xcite Simulation Acceleration

Xcite Benefits High Performance Up to 100K cycles per second in simulation acceleration performance High Capacity Up to 10M ASIC gates capacity; 20M gates in twin-box configuration Fits in Existing Design Environment Accelerates RTL and gates Supports full Verilog language constructs and PLI calls Advance Debugability RTL debugging with software simulation flexibility Real-time hot-swapping from accelerated simulation to software simulation for maximum performance and debugability Access to all design node history data during or after simulation with VCD-on-Demand Resource Sharing Sharable among multiple users in a design team

Verification Bottleneck
The best method to verify complex designs is to simulate all possible conditions. But as design complexity increases, the productivity gap widens between what can be designed versus what can be verified. Traditionally, Software simulators are known for their robust design debug abilities, but at the cost of simulation performance; hardware emulators are known for high performance at the cost of poor design debugging capabilities. To close the productivity gap, Verisity has developed the most advanced verification product on the market today.

Xcite
Xcite, based on Axis' patented ReConfigurable Computing (RCC) technology, delivers simulation and acceleration in a single system using one design database. Xcite offers simulation performance of up to 100K cycles/second on a design capacity of up to 10M ASIC gates, while preserving the native software simulation debugging environment. With Xcite, designers can now achieve full system verification with the same flexibility and ease of use that is inherent to software simulation.

Xcite provides true RTL simulation acceleration, directly mapping RTL constructs onto the RCC elements. Unlike other solutions, Xcite bypasses logic synthesis in order to preserve design debugging at the RTL level. As a result, simulation with Xcite looks, acts, and feels identical to software simulation at hardware speed.

Xcite comes in two configurations; Xcite-1000 and Xcite-2000; both delivering the same level of performance. Xcite-1000 has maximum capacity of 2M ASIC gates and fits directly into the workstation via the PCI bus, eliminating the need for external chassis or cables. Xcite-2000 has maximum capacity of 10M gates and connects directly to the workstation through one set of PCI extender cable. Both provide the highest performance communication between the workstation and the RCC acceleration engine.

Transparent RCC Acceleration
Xcite tightly integrates the RCC software simulator -- Xsim -- with RCC hardware into one unified package. The RCC accelerator is based on the most advanced FPGA integrated circuits containing 100s of 1000s of mini co-processor elements. These co-processors are uniquely configured for every design and executes in a massively parallel architecture delivering the best possible performance for simulation acceleration. Because Xcite supports same RCC state representation in software simulation and acceleration, designers can easily move from simulation to acceleration, using single database and one user environment.

One Step Compilation and Mapping
Design description can be separated into three components: behavioral, RTL and gates. The Xcite compiler automatically maps sections that can be RCC accelerated -- RTL and gates -- and builds a native compiled simulation image for behavioral sections that will stay in Xsim.

Using its patented “Hierarchy Extracted” mapping technique, the Xcite compiler automatically maps the design onto arrays of FPGAs for optimized gate usage and high performance simulation.

Absolutely No Compromises
Because Xcite is an event-driven simulator, it supports all design style including asynchronous logic and feedback loops. Additionally, Xcite is fully compliant with IEEE 1364 Verilog HDL language standard so there are no restrictions on the language support regardless of its abstraction level.

Debug in Software, Accelerate in RCC
One of the unique capabilities of Xcite is its ability to swap states between Xsim and RCC acceleration in real time. During simulation, the user may elect to swap all RCC state into Xsim to debug the design and continue in software simulation. Once the circuit is fully debugged and problem isolated, the simulation state value can be swapped back into RCC acceleration for maximum simulation performance.

This allows users to simulate as fast as possible to the point of design error, and then swap out the simulation state into Xsim for design debug. Within the debugging environment, designers have 100% node visibility and access to all Verilog language commands.

In addition, the ability to swap between Xsim and RCC aids in system bring-up process by allowing users to initialize the design in 4-state Xsim software simulation and then swap into 2-state RCC acceleration for maximum performance. This capability significantly reduces the design bring-up effort compared to other hardware solutions.

Extract complete history without re-simulation
Either during or after simulation, Xcites’ VCD-on-Demand (VoD) capability can extract all node history values from any point in simulation without re-simulating from time zero. This capability significantly increases designers' debugging productivity.

Incremental Compilation
Turnaround time for design changes is highly efficient with incremental compilation. For small design changes, complete turn-around time can be less than half an hour for designs greater than one million gates.

Simplified Library and Memory Conversion
In order to maximize density and performance on RCC co-processors, design library and memory cells need to be converted into Xcite RCC elements. For library cells, the conversion process involves a simple process of executing library compiler, which automatically generates the appropriate mapping along with library verification test vectors.

For embedded design memory blocks, Xcite-2000 has on-board memory that can be personalized to the specific memory type. Furthermore Xcite-2000 offers the capability to simulate large external memories by using workstation memory and communicate via the fast PCI bus for complete system verification.

All Encompassing System
To stay one step above your competition, you need the most efficient verification tool that will fit directly into your design environment. Xcite offers the highest simulation performance of 100K cycles/sec along with a capacity of up to 10M ASIC gates, while preserving the native software simulation debug environment.

Xcite Specifications
RCC Configurations	Xcite-1000: Fits in PCI slot of Sun workstation Xcite-2000: External chassis connected via PCI bus
XsimSoftware Simulator	Native compiled code simulator Supports all Verilog constructs + PLI
Performance	Up to 100K cycles/sec
Capacity	Xcite-1000: Up to 2M ASIC gates Xcite-2000: Up to 10M ASIC gates Xcite-2000-Twinbox: Up to 20M ASIC gates
Memory	Up to 192M bits of on-board memory Up to 4G of workstation memory
Debug	Native Verilog interface All internal nodes visible Real time simulation state swap between software and hardware
Design Format	IEEE 1364-2001 Verilog
Platform	Sun Ultra 60 Sun Ultra 80

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