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Specman Elite
With Verisity's Specman Elite, you capture the rules from
the specifications and use this info to automate the functional
verification process. Specman Elite's methodology finds
the "bugs you haven't thought of" in your Verilog or
VHDL design -- caused primarily by ambiguities in the spec,
or unanticipated usage by the target system. The result?
Faster verification and higher quality products. Get working
silicon to market on time! (New!
Specman Elite SureCov Integration Flash Demo)
vManager
Verisity’s vManager is the industry’s
first solution that automates the management of complex
verification projects and guides verification from planning
and goal setting, to closure. vManager
automates the deployment of simulation runs, analyzes failures
and coverage data and controls the steps towards closure.
eAnalyzer
eAnalyzer is an intuitive static
analysis and methodology tool that simplifies verification
environment development with a unique combination of rules
and methodology checks; including Verisity’s e
Reuse Methodology (eRM™) compliance
reporting and Coverage-Driven Verification (CDV) guidance.
eCelerator
eCelerator uses innovative synthesis
technology to transform the most frequently executed portions
of your e testbenches for acceleration
via hardware. By shifting the computationally most expensive
parts onto hardware, you can achieve significant performance
gains in your verification- from 10x to 50x or more. Regression
runs which can take weeks to complete can now be finished
in hours. And since part of your testbench remains on the
workstation, all the features of Specman Elite are accessible.
SureCov
SureCov gives you the fastest, most complete code coverage
capability on the market. With Verisity's SureCov, you see
graphically which modules have been sufficiently exercised
and which require additional effort. With this measure of
effectiveness of your functional test suite, you can predict
how much effort remains and your verification engineers
can clearly see which sections of the design have not yet
been adequately covered.
(Download) (New!
SureCov Flash Demo)
sVM
– System Verification Methodology
The System Verification Methodology (sVM)
is a prepackaged verification knowledge-transfer system
that provides 10x automation power for SoC and system-level
designs. sVM includes powerful multi-channel
generation based on Verisity’s highly successful Specman
Elite™ testbench automation. sVM
is an integral part of a complete Verification Process Automation
solution.
eRM
– e Reuse Methodology
Verisity’s eRM provides dramatic
functional verification productivity gains for advanced
ASICs and SoCs through it’s comprehensive set of best-known
methods for eVC development practices.
eRM allows engineers to achieve consistency
when developing their own eVCs or
using those obtained from external sources. By following
the step-by-step guidelines and common usage model set forth
by eRM, engineers save verification
time and effort, and are seeing significant quality improvements.
eVC–
e Verification Component
Verisity and partners provide "e" Verification
Components (eVCs) also known as VIP. These components
are pre-verified, reusable verification IP that
drastically cut down the
time it takes to create your verification environment. They
are based on Verisity's high-level verification language,
e, so you know they'll work with
Specman Elite right from the start. By incorporating eVCs
into your design, you find more bugs, faster. Almost all eVCs are now eRM compliant, so they're guaranteed to plug and play together.
Xsim
Xsim is a high performance native compiled code event based
HDL simulator that is included in Xcite, Xtreme, and XoC
packages. Xsim supports mixed Verilog, VHDL, and SystemC
languages, and has a supported interface to Specman Elite.
Xsim is over 6 years old and has successfully executed numerous
designs in the 30-50 million gate range.
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XoC
XoC™ is an all-inclusive, unified verification system
for ARM microprocessor-based designs that reduces communications
overhead and eliminates time-intensive integration efforts
for design teams. XoC enables the smooth transition between
all nine different operating modes from block-level testing
through application software and features a Co-Verification
Debugger that creates a common communication environment
between hardware and software teams through AMBA™ transactions.
Xtreme
Xtreme® offers simulation, acceleration, emulation,
and hardware/software co-verification, in a unified, compact,
server-sized system, at speeds of up to 1 million cycles
per second on designs of up to 100 million ASIC gates. Xtreme
provides full debugging capabilities throughout the entire
verification flow, allowing emulation to start much earlier
in the design cycle.
Xcite
Xcite® offers simulation acceleration performance of
up to 100,000 cycles per second on designs of up to 10 million
ASIC gates. Xcite delivers hardware performance with software
debugging capabilities. Designers can run simulation as
fast as possible while quickly detecting and isolating design
problems.
Xtreme-II
Xtreme-II offers Platform Verification, a unified verification
environment designed to enable a platform-based design flow.
Leveraging the patented ReConfigurable Computing (RCC) technology,
Xtreme-II offers the best solution for simulation, acceleration
and emulation in one unified system. By leveraging the latest
FPGA technologies, Xtreme-II delivers fast runtime performance
and the highest capacity, while preserving the native RTL
simulation debugging environment.
Xtreme
Server
The Xtreme Server is a multi-session, next-generation acceleration
and emulation solution that meets the requirements for high-performance
chip- and system-level verification. It offers simulation,
acceleration, emulation and hardware/software co-verification,
in a unified, compact, server-sized system, at speeds of
up to 1 million cycles per second on designs of up to 100
million ASIC gates.
Xpert
Xpert™ for ARM processors is an integrated co-verification
tool for designs utilizing ARM microprocessor cores and
Verisity's ReConfigurable Computing (RCC) platform for design
verification. It provides simulation models and software
debugging tools to isolate and fix even the most complex
errors. Xpert for ARM processors provides the best balance
of visibility, control, and performance for integrating
software and hardware in an easy to use environment.
MHDL
Language-neutral versions of the XoC, Xtreme and Xcite product
families address the needs of today's language-neutral customers.
XoC, Xtreme and Xcite enable customers to directly accelerate
and emulate their mixed-language RTL designs, while providing
access to all of the debugging capabilities that exist in
the Verilog-only versions, such as hot-swapping and VCD-on-Demand.
Verification
Advisor
Verisity's Verification Advisor is a dynamic web-based knowledge-transfer
system for verification engineers. Various techniques or
``best practices" are summarized as patterns and supported
with examples in "e". This
concept transfers lessons learned across multiple disciplines.
New users pick up skills from experienced professionals
while experienced verification engineers share information.
Verification Advisor helps you capture, present, and distribute
the principles of verification.
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