sVM System Verification Methodology

System Verification Methodology New methodology targeted at SoC and system-level verification Encapsulates comprehensive guidelines for SoC verification Unique combination of technology including, libraries, analyses, methodology and language Utilizes Specman Elite's powerful multi-channel generation Supports Verification Process Automation (VPA) based solutions

Do you need advanced verification methodologies that tackle tough SoC designs? Having trouble developing a chip-level environment that can verify more than one interface at a time? Are you struggling with proliferating best-practices? Are you searching for an out-of-the box solution that delivers results? Verisity has developed the System Verification Methodology (sVM™) that delivers prepackaged expertise and proven automation power.

Verification Process Automation (VPA) Support
The System Verification Methodology (sVM) is a prepackaged verification knowledge-transfer system that provides 10x automation power for SoC and system-level designs. sVM includes powerful multi-channel generation based on Verisity's highly successful Specman Elite™ testbench automation. sVM is an integral part of a complete Verification Process Automation solution.

Complete Verification Process Automation (VPA) solutions offer 10x automation power plus process encapsulation.

Higher-Levels of Abstraction
sVM provides the conceptual and generation power required to verify the simultaneous behavior of more that one interface at a time. It eliminates the need to manually code the highly complex task of correctly controlling the interaction of generation on multiple interfaces. The sVM methodology is also highly scalable and adaptable to distributed verification and design team needs.

Advanced Capabilities Delivered in sVM
sVM includes a set of comprehensive guidelines and best practices to help every level of engineer. These guidelines are the product of several years of working with leading customers producing highly complex designs. sVM also leverages new multi-channel technology in Verisity's Specman Elite that makes it possible to achieve the same goals in one-tenth the number of verification cycles. Multi-channel technology coupled with library enhancements for configurable SoC design allows for simple adoption and increased automation.

Multi-channel sequence generation combined with the visualization toolkit slashes SoC verification development time.

Multi-Channel Generation
Multi-channel generation automates the generation of realistic system-level "scenarios" to test complex SoCs. It also allows for easy composition and analysis of the interactions between multiple interfaces, eliminates wasted simulation cycles, and ensures verification of corner cases at the SoC level. New multi-channel constraint solver technology optimizes use of chip-level verification cycles and provides specialized algorithms to ensure scalability of capacity and performance and improves time-to-verification closure.

sVM Library Enhancements
sVM includes a collection of building blocks in a library commonly required for verification of a multi-channel Soc. The initial entry is a register model, used commonly for mirroring the configuration and status registers (CSRs) of devices. The register model replaces the need to develop the basic capabilities of any register in the verification environment, and supports the many important traits of sVM.

Visualization Toolkit
The Visualization Toolkit is key technology for supporting the complex high-level debugging process. It provides a window into higher-level constructs, and detailed information for debugging the behavior of the verification environment and the Soc. It also allows the unique ability to visualize the sequence generation timing and interactions across multiple channels.

The Next Step in Verification Process Automation
sVM is an integral piece of a complete VPA environment. The ability to deliver proven module and chip-level verification and proliferate those practices to the SoC and system-level is invaluable. sVM's out-of-box, prepackaged expertise delivers the foundation and productivity enhancements you need to get your next design verified.

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