SureCov
Fast, Complete Code Verification |
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Verisity at a Glance
Are you looking for a comprehensive verification solution?
Verisity is the verification company of choice for leading
SOC semiconductor companies, system manufacturers, communication
startups, and star IP providers.
SureCov Product Overview
Verification metrics are key to making the right
tape-out decisions. Verisity's SureCov gives you
a way to clearly measure the effectiveness of your
test suite on your HDL implementation.
SureCov empowers your verification engineers to:
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Effectively manage and measure their code
verification progress and gauge the remaining
effort
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Quickly pinpoint areas of the design which
have not yet been adequately covered and need
additional testing
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Identify any excess logic or potential holes
in a functional test plan |
SureCov, part of Verisity's suite of verification solutions,
including eVC, Specman Elite,
and Verification Advisor, gives you the fastest,
most complete code verification capability in the market today.
Performance: Fast, Faster, Fastest
SureCov's unique approach to code verification utilizes
native Verilog to instrument and analyze the source code without
burdening the simulator. This patent-pending technology can
achieve up to 4X better performance (i.e. lower overhead)
than other coverage tools, while supporting all the leading
Verilog simulators.
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Highlights
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- Fastest Code Coverage Engine on the Market
- Easy to Use, Very Intuitive
- Industry's Most Comprehensive Feature Set
Features
Platform and Simulator Support
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With the release of version 3.0,
SureCov increases its performance lead with the introduction
of re-instrumentation. With this feature, users of
SureCov can dramatically reduce the time it takes to reach
their overall coverage target. The speedup is proportional
to the coverage attained and is attributed to removing
coverage tracking on already covered HDL code. For example,
if a user has reached 80% of their code coverage target,
re-instrumentation removes code coverage metrics for items
already covered (thereby reducing up to 80% coverage overhead),
leaving only the remaining 20% to track the remaining
coverage holes. The user benefits by being more productive
and being able to close the loop on regression testing
sooner.
Intuitive Graphical User Interface
(GUI)
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SureCov empowers users with intuitive
features to help engineers work faster and
smarter.
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SureCov's graphical user interface makes it easy
to understand the effectiveness of your test suite
and shows which sections of the design remain to
be adequately covered. It provides easy-to-use mechanisms
to help you focus on the problem areas. Here's how:
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COLOR CODING of the HDL source provides quick
feedback on areas that need to be improved
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COVERAGE LOCATOR BAR provides a color spectrum
index into your code (right margin bar)
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CROSS PROBING allows easy referencing between
HDL source code and your FSM via Suresight's
automatic generation of FSM bubble diagrams |
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SEARCH by text or by coverage selection and
stepping through each finding
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Block and Arc Coverage
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SureCov makes it easy to understand the
arcs (code branches) that have been taken
and others which need additional testing -
so you can be even more productive.
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A block is defined as a sequence of HDL code that
contains no branches (arcs). If the first line of
a block is executed, then all lines of the block
are executed. Block coverage, in effect, provides
essentially the same information as line coverage,
with less overhead. Arcs are typically created by
Verilog case or if-then-else statements. Arc coverage
is different from block coverage because arcs specify
how simulation control entered a block.
SureCov displays block and arc coverage highlighted
right in your code where it belongs. SureCov colors
the lines entirely tested green, and those untested
red. Code that has been executed at least once--but
not from all possible arcs based on the control
flow of the code -- is colored yellow.
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Automatic FSM Analysis - state, transition
and sequence
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A picture is worth a thousand words and
with SureCov, you get automatic FSM extraction
for easy visualization to help you eliminate
mistakes along the way.
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By automatically recognizing and extracting Finite
State Machines from synthesizable RTL, SureCov eliminates
the tedious manual preprocessing required by other
tools. FSMs are displayed as bubble diagrams without
any user intervention. SureCov depicts the states
and transitions in clear colors indicating if they
are fully covered, not covered, or partially covered.
To highlight problem areas, SureCov also distinguishes
unreachable, redundant, and terminal states using
orange, blue, and rectangles respectively. The user
can define paths through FSMs and query the SureCov
database to check coverage for a particular FSM
sequence.
SureCov supports both Mealy and Moore machines
and a variety of state variable encodings: regular
state vector, one-hot state vector, individual scalars
for each vector, and others.
For coding styles which are not commonly used and
non-synthesizeable, such as data-flow design descriptions,
SureCov enables FSM extraction through source code
directives.
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Comprehensive Event & Expression
Coverage
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SureCov's expression coverage quickly
pinpoints On and Off product terms to help
you verify your covered conditions more thoroughly.
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SureCov event coverage measures if each event has
triggered and caused the execution of the procedural
block to continue.
For expression coverage, SureCov allows you to
determine which term(s) in multi-term expressions,
contribute to a true value for the expression's
On Products and which term(s) contribute to a false
value for the expression's Off Products. A minimized
sum-of-products is provided for each expression.
SureCov displays expression and event coverage right
in the code or, by clicking on the source, takes
you to the detail of the expression terms. SureCov
enables three modes of expression coverage: only
On Products, both On and Off Products, and Exclusive
On/Off Product evaluation. For all three modes of
operation, SureCov supports variable-width expressions.
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Accurate Toggle Coverage
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SureCov's toggle coverage gives you the
right level of detail to help you isolate
the problem more easily.
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SureCov's toggle coverage
can measure three forms of toggle coverage: simple
assignments, value toggle, and strict toggle. In simple
assignments, toggle coverage tracks whether each port,
register, and wire has been driven to a known (non-X)
value during simulation. It tracks whether each bit
of each signal has reached either a low value or a
high value during simulation. This is useful for early
detection in the design process to ensure that all
module ports, declared registers, and wires have been
assigned to a known value and have come out of the
unknown (X) state. Value toggle coverage expands all
vectors into bits and verifies that each bit has been
assigned to both 0 and 1. Value toggle coverage is
useful late in the design process to verify that all
bits have been (and can be) driven to both a logical
0 and a logical 1. For greater precision and accuracy,
SureCov provides tracking of positive edges (0-1)
and negative edges (1-0) through its strict toggle
coverage option. |
Flexible Instrumentation Control
The instrumented design is used in place of the original
Verilog during simulation to track coverage. Running SureCov
is simple - just type SureCov plus the standard Verilog
options (-f, -y, -v, +libext+, etc.). No additional SureCov
options are required. For added flexibility, SureCov supports
partial instrumentation by allowing designers to enable
and omit design libraries, modules, and instances as well
as enabling and disabling select coverage types. This
allows designers to further focus on the design areas
important to their task.
Advanced Simulation Control
SureCov has advanced simulation control such as features
which enables users to specify coverage start/stop times,
write coverage databases at specified times (coverage
checkpointing), and query code coverage metrics during
simulation (dynamic coverage feedback). With this information,
designers have even more control over their coverage tracking
process, thus enabling them to better focus and direct
simulation coverage on the areas that need it most.
Powerful Test Suite Ranking and
Merging Capability
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Test ranking and merging of different
coverage databases is easier and more intuitive
with SureCov.
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SureCov has powerful utilities for test suite ranking
and merging. Test suite ranking is useful for regression
test selection or test time optimization. Users
can quickly import test suites into SureCov and
rank them based on any combination of coverage types.
SureCov ranking helps to:
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Identify tests that do not provide additional
coverage
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Identify which tests achieve the most coverage
in the shortest amount of simulation time
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SureCov allows users to obtain incremental coverage
results for a particular test or series of tests,
or obtain a cumulative coverage measure for a series
of tests.
For test merging, Surecov uniquely combines coverage
results from databases of different coverage types,
databases of design modifications, or different
design databases altogether.
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Extensive Test Reporting
SureCov reporting lets you create a variety of reports
such as summary, detailed, filtered, and hit count. SureCov
reporting can be used in either textual or graphical mode.
The textual mode is ideal for generating quick summaries
or detailed textual reports. The graphical interface is
used for analysis and investigation of the textual reports.
For example, summary reports show the overall coverage
statistics for the design. Detailed reports provide insight
into the design for each coverage type: block, arc, FSM
state, FSM state transition, expression, event, and toggle.
In addition, users can access coverage statistics per
module and per instance.
For more accurate and flexible reporting, SureCov allows
users to focus only on design elements that are important
to them but filter out unimportant coverage types or irrelevant
design areas for code verification such as default states
or embedded IPs, respectively.
Insightful Hit Count Statistics
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Hit count with SureCov uncovers not only
areas that need additional tests but also
areas that may have redundant tests. With
SureCov, you can reach your quality goal faster.
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Hit count enables users to define how many times
a design element must be "hit" before it is considered
covered.
This gives users insight into the activity level
of their testbench, helping them to tune and achieve
optimal performance of a given testbench.
This is yet another way to ensure a thorough coverage
methodology and grade the quality of your testbench.
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Simulator
SureCov supports Verilog-XL, NC Verilog, VCS, Polaris,
ModelSim, and Silos III simulators.
Platform
SureCov supports Linux, HPUX, and Sun Solaris operating
systems.
Contact Us
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