| Verisity's Language-Neutral Acceleration and Emulation
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Introduction
Throughout the 1990s, the high-level description languages used in
electronic system and system-on-a-chip (SoC) designs were either VHDL
or Verilog. A constant debate about which language would prevail existed
for several years. But today, the language war between VHDL and Verilog
has come to an end, and complex chip designs use both VHDL and Verilog.
One of the driving forces behind language-neutral design is the
integration of various IP into SoC designs. This IP can come from
many sources, both internal and external to the company, and can
be represented in Verilog or VHDL. Another force is the constant
consolidation of companies. As companies go through mergers and
acquisitions, they end up with design teams using both VHDL and
Verilog. The language-neutral requirement is particularly true for
those companies with design centers in Europe and the U.S. Rather
than force one design team to adopt the other language, most companies
look to tool vendors to support a language-neutral environment.
Figure 1. Typical SoC Design Verification Environment
When verifying a system or SoC design implemented with a mixture
of VHDL and Verilog, a language-neutral simulator, accelerator,
and emulator are needed. As designs get more complex and their verification
more challenging, designers are turning to hardware-assisted verification
methodologies, such as acceleration and emulation. Verisity supports
language-neutral capabilities in all of its acceleration and emulation
product families (XoC, Xtreme and Xcite) to address these needs.
XoC, Xtreme and Xcite Product Families
XoC, Xtreme, and Xcite, are based on Axis' patented ReConfigurable
Computing (RCC) technology. Each consists of a single system with
one design database that can be used from software simulation to
acceleration to in-circuit emulation. These products enable a smooth
transition between each phase of verification. The ability to swap
between the hardware verification engine and the software simulation
engine on-the-fly enables designers to run at hardware speed while
debugging in a familiar software environment.
Advanced debugging capabilities, such as VCD-on-Demand (VoD), enable
XoC, Xtreme, and Xcite to capture all activity for all signals during
a single simulation. During debugging, any signal in the design
can be recalled at any point in simulation time without having to
re-run simulation, thus improving the number of debugging cycles
that can be completed and increasing overall verification productivity.
Figure 2. VoD Shortens Debugging Cycle
XoC, Xtreme and Xcite support direct RTL acceleration and emulation.
Designers simulate, accelerate, emulate, and debug at the RTL without
having to synthesize their design to gates or debug an unfamiliar
gate-level netlist.
The unified methodology supported by XoC and Xtreme systems reduces
the risk of errors introduced during various phases of verification
and reduces the cost of setup when bringing up in-circuit emulation.
By supporting a single database, no translation is required when
moving from software simulation to acceleration to emulation. More
so, designers have access to all software debugging capabilities
and a familiar environment throughout the flow.
When bringing up in-circuit emulation, the unified methodology
and in-circuit verification flow reduces the amount of risk, resources,
and time required to bring up an in-circuit emulation setup. For
more information on in-circuit verification (ICV), please refer
to the technical whitepaper "In-Circuit Verification: Unifying
Simulation and Emulation."
Language-Neutral Extension To XoC, Xtreme
and Xcite
The XoC, Xtreme and Xcite product families can accept designs written
in both VHDL and Verilog. Designs can contain arbitrary mixtures
of VHDL and Verilog (for example, a VHDL testbench with a Verilog
design-under-test with VHDL IP).
The XoC and Xtreme families support direct RTL acceleration and
emulation, as well as RTL debugging capabilities, unlike other acceleration
and emulation solutions that require mapping of the RTL to gates
and debugging at the gate-level for language-neutral designs.
Figure 3. Common Method for SoC Design Verification
The language-neutral families of XoC, Xtreme, and Xcite support
all existing debugging capabilities in both languages, such as hot-swapping
and VoD. Designers have access to all signals at all times, with
no language restrictions.
Figure 4. Unified Methodology for the Language-Neutral World
The core technology of XoC, Xtreme and Xcite -- Our patented RCC
technology -- enables co-processors in the Verisity hardware to
be reconfigured for a particular task, such as adapting the hardware
for Verilog or VHDL, or both.
Xsim
Verisity's software simulator, Xsim, is tightly linked with the
RCC hardware and is used as the front-end to the acceleration and
emulation environment. The compiler maps the Verilog or VHDL design
to an internal database used for acceleration and emulation. The
compiler takes the RTL design, regardless of the language, and configures
it to the RTL tasks executed by the RCC engine. Because the hardware
is on-the-fly reconfigurable, there is no need to redesign the hardware
engine.
The language-neutral families of XoC, Xtreme and Xcite support
the 1076-1993 IEEE VHDL Standard and the 1364-1995 and –2001
IEEE Verilog Standards. They also support a common graphical user
interface (GUI) and command-line interface (CLI) for Verilog, VHDL,
and the mixed-language environment. For integration with C models
and other third-party tools, Axis' products support the programming
language interface (PLI) for both Verilog and VHDL blocks.
Figure 5. Language-Neutral User Interface
Summary
Verisity's language-neutral versions of the XoC, Xtreme and Xcite
product families address the needs of today's language-neutral customers.
XoC, Xtreme and Xcite enable customers to directly accelerate and
emulate their mixed-language RTL designs, while providing access
to all of the debugging capabilities that exist in the Verilog-only
versions, such as hot-swapping and VCD-on-Demand.
The single-platform, single-database architecture of XoC, Xtreme
and Xcite supports a unified methodology, which enables a smooth
transition from simulation to acceleration to in-circuit emulation.
This methodology improves overall verification productivity and
reduces the risk of errors introduced between each phase of verification.
With Verisity's language-neutral solution, designers can increase
productivity, gain higher confidence in their designs, and get products
to market much faster than ever before.
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