e Verification Components Reusable Verification Environments Save Time, Improve Product Quality

e Verification Components (eVCs), sometimes referred to as verification IP (VIP), are reusable, configurable, pre-verified, plug-and-play verification environments. They offer the easiest to use, most complete module, chip and system level verification solution available. eVCs integrate automatic stimulus generation, assertion checking, and functional coverage analysis all within in a single, extensible component. eVCs drastically reduce the time needed to compose a verification environment. The philosophy underlying eVCs differs significantly from competing VIP products. Rather than use thousands of directed tests, eVCs employ automatic generation and a coverage driven methodology. Using automated scenario generation the eVC can typically achieve 90-95%+ coverage of the protocol. With the addition of a few tests the remaining corner cases are then exercised. This approach uncovers more bugs faster and frees engineering time to focus on testing the DUT's proprietary functionality.

Quality and Productivity Gains
With eVCs verification environments are created in days instead of weeks or months. You can begin writing tests much earlier and achieve a much higher quality product. Furthermore, Verisity's Verification IP can be reused without expending any extra effort. This enables you to retain your investment when moving from module to system level verification as well as when verifying derivative products. Follow the success story link to see how STMicroelectronics benefited from using the AHB eVC.

Nearly 25 e Verification Components Available
There are now near 25 e Verification Components available commercially from Verisity and our Verification Alliance partners. To help you locate the eVCs you need see the list of the commercial eVCs below.

The eRM Compliant logo indicates that the eVC has complied with the e Reuse Methodology requirements. This ensures that the eVC has been built to Verisity's exacting standards and will plug and play with other eRM compliant eVCs.

Cold Spring Engineering (info@coldspringeng.com  •  www.coldspringeng.com)

Globetech Solutions (info@globetechsolutions.com  •  www.globetechsolutions.com)

IrDA	Now	Verifies IrDA PHY 1.4 SIR/MIR/FIR (V-FIR soon). Supports random and directed infrared frame generation, error injection, timing, protocol and data checking. Includes high-level tools for local host stimulus generation and interface cross-checking.
UART	Now	Verifies all UART devices. Supports random and directed UART frame generation, error injection, protocol and data checking. Provides additional device-level verification capabilities for 16x50 (fast) UART. Includes high-level tools for local host stimulus generation and interface cross-checking.

HCL Technologies Limited. (Ashok@noida.hcltech.com • www.hcltech.com)

HDL Design House (info@hdl-dh.com • www.hdl-dh.com)

Registers	Now	Represents register maps, registers and register fields. Supports variable register/field width, access by name/address, and various types of field kinds and reset types. Package is released under GPL.
I2C	Now	I2C 2.1 compliant eVC supports general call addressing, 10-bits addressing, standard/fast/high speed modes, and can implement all I2C device types: masters, slaves and master-slaves.
SATA	Now	SATA/SATA II compliant, supports legacy ATA commands, port multiplier and port selector, and comes with rich sequence libraries for all protocol layers.
HDH JTAG (HDH 5000)	Now	Compliant to IEEE 1149.1-2001 Standard. Supports all mandatory and optional protocol instructions. Extendable with user defined instructions and registers. Supports optional reset signal.

Intelliprop Inc. (amits@intelliprop.com •  www.intelliprop.com)

SATA	Now	Generates SATA-I and II compliant frames, and sequences as Host or Device. Includes protocol and temporal checkers and a passive monitor for coverage. The eVC is eRM compliant and contains hooks for expansion and scoreboards.
SAS	Now	Generates SAS Rev 3b Protocol Frames at the transport layer (and below). Can be configured as TARGET or INITIATOR; the eVC has programmable port and phys for multi-port/phy combinations. Temporal, protocol and coverage checkers are built into the monitors. The eVC is eRM compliant and contains hooks for easy expansion and scoreboarding.
Future plans	Inquire	Fibre Channel, SCSI, and ATA models.

Paradigm Works (info@paradigm-works.com  •  www.paradigm-works.com)

Gigabit Ethernet

Now

Supports 10Mbps to 10Gps, other interfaces include: MII, RMII, GMII, RGMII, XGMII, XAUI, XSBI and MDIO.

Tata Elxsi (nath@tataelxsi.co.in  •  www.tataelxsi.com)

LIN

Now

Compatible with Local Interconnect Network (LIN) Rev. 1.3 and 2.0. Supports Unconditional, Event-triggered and mandatory Diagnostic frames for both master and slave configuration.

YogiTech S.p.a. (contactus@yogitech.com  •  www.yogitech.com)

CAN 2.0B	Now	Verifies Controller Area Network (CAN). Provides protocol testing and monitoring as well as the ability to define real frame data and monitor the DUT's response.
ATAPI 6 Host	Now	Implements an Ata/Atapi Host 6 with supports of PIO, Multiword DMA and Ultra DMA transmission mode. Delivered with full Ata 6 command database and Atapi packet commands for multimedia devices. Provides protocol testing and monitoring, with built in coverage of bus traffic. Also includes a full test suite.
ATAPI 6 Device	Now	Implements Ata/Atapi 6 Device with support of PIO, Multiword DMA and Ultra DMA transmission mode. Includes full Ata 6 command database and Atapi packet commands. Provides protocol testing and monitoring, with built in coverage of bus traffic. Also includes compehensive sequence library.
OCP 2.0	Now	Verifies the Open Core Protocol (OCP) interface. The OCP 2.0 eVC, eRM compliant, can be used for verification of any OCP interface across all levels of abstraction and it is suitable for multi OCP interface systems.
LIN	Now	LIN 2.0 eVC is the most reliable solution for the verification of LIN IP and LIN networks. The highest functional coverage is achieved by a complete built in set of predefined coverage items. The eVC also embeds a powerful protocol checker fully compliant with LIN 2.0 specification. LIN 2.0 eVC includes a database of LIN frames easily constrainable to match real frames and an extensive test suite covering the majority of the possible LIN scenarios. A Node Capability file parser is also provided to enable a rapid and easy configuration of the eVC. Combined with the automatic configuration of the LIN network, first test can be launched very rapidly by the user.

Verisity Design (sales@verisity.com  •  www.verisity.com)

AMBA AHB	Now	Verifies any device in an AMBA AHB bus environment, including masters, slaves, arbiters, decoders, or any combination. Verisity/ARM have worked together to ensure accurate protocol modeling. This eVC uniquely works with ARM's AMBA Compliance Testbench (ACT).
AMBA AXI	Now	Verifies any device under test (DUT) in the AMBA AXI bus environment. Supports the verification of all AXI bus based devices including masters, slaves and interconnect. Provides data generation, protocol checking and functional coverage.
PCI Express End Point  new!	Beta Now	Fully verifies all three PCI Express layers in PCI Express end point DUTs. Compliant to the PCI Express Base specification revision 1.0a. Provides the most complete verification environment available for PCI Express including full functional coverage and constrained random generation. Provides built-in checking and coverage to validate against the Intel PCI Express compliance checklist.
PCI Express Root Complex  new!	Beta Now	Fully verifies all three PCI Express layers in PCI Express root complex DUTs. Compliant to the PCI Express Base specification revision 1.0a. Provides the most complete verification environment available for PCI Express including full functional coverage and constrained random generation. Provides built-in checking and coverage to validate against the Intel PCI Express compliance checklist.
PCI 2.2 & 2.3	Beta Now	Includes PCI master and target device models and a protocol and timing monitor to report protocol violations. Also includes a comprehensive test suite covering all protocol scenarios outlined in the PCI SIG's PCI 2.2 and 2.3 specification compliance checklists.
Ethernet (10/100/1G/10G)	Now	Verifies any IEEE802.3: 2000 and IEEE Draft P802.3ae/D4.0 compliant MAC or PHY device, and provides extensive sequence library for verifying interfaces viz. 10Mbps, MII, GMII, RMII, SGMII, TBI, XGMII, XAUI, XSBI.
USB	Now	Supports USB specification revs 1.1 and 2.0. Functions as one or both of USB Host and/or USB Device. Runs at high, full or low speed. Supports up to 127 devices. Supports the UTMI and UTMI+ interfaces as well as On-the-Go (OTG).

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